The present invention relates to communications systems, and particularly to communications systems where the data is synchronously formatted in frames.
Many very widely-used communications protocols require the data to be synchronously formatted in frames. Two very important protocols of this type are the "T1" standard, which is the first-level standard high-speed data interface to the telephone network in the United States and Canada, and CEPT, which is the comparable standard in Europe. Receivers for communications of this type must be able to extract the timing from the incoming signal, so that the incoming data is correctly sampled. Sampling with improper timing can lead to data errors.
T1 is an alternate-mark-inversion (AMI) format, where each "1" data bit is represented by a pulse, and a "0" bit is represented by the absence of a pulse. (The pulses are of alternating polarity, so that the time-averaged voltage of the signal is equal to the level of a "0" bit.)
When a T1 signal is received, the receiver must extract the correct stream of "1" and "0" bits from the incoming analog signal. To do this, the receiver must not only be able to correctly interpret the incoming voltage levels, but must also be able to sample the incoming signal at the correct instantaneous times. The T1 format guarantees that the average data frequency will be 1.544 MHz, but the receiver must also be able to "fine-tune" itself to the actual data frequency of the incoming signal. Moreover, it is not enough to sample the incoming signal with the correct frequency: the receiver must also be able to follow the phase of the incoming signal. For example, if the incoming signal is sampled on a pulse edge, the receiver could mistake a "1" bit for a "0" bit.
Thus, a T1 receiver must be able to recover a correct clock signal from the incoming synchronous data signal. However, this presents further difficulties. The incoming data stream may include random small shifts in the apparent delay between successive symbols. Since the clock must be recovered from the data, this can lead to significant phase modulation of the clock. This undesirable phase modulation of the clock is known as jitter. This jitter can become quite large in T1 communications systems, since a T1 span may include several repeater stations which are typically based on a LC tank circuit. Typically the jitter may be magnitude- and frequency-dependent.
A well known technique to filter out this jitter is to write the jittered data into a small FIFO, using the coherent recovered clock (which includes jitter), and read the data back out using a stable reference clock. (The reference clock is phase locked to the write clock, but filters out the jitter.) Such a "rubber band" use of a FIFO is sometimes referred to as an elastic store.
The present invention provides an improved communications receiver for formats where the clock must be recovered from the data. The amount of jitter present in the data is measured by using the read clock as a reference to sample the FIFO address pointers. This provides a measurement of instantaneous jitter magnitude.
The improved measurement of jitter magnitude permits slight frequency offsets to be detected and tracked. This measurement can also be used, in subsequent processing stages, for such purposes as analysis of data errors, checking a data source for loss of T1 compatibility, or adaptive monitoring of channel characteristics.
FIG. 2A shows a conventional jitter-measuring system. A first-in-first-out memory ("FIFO") clocks in a received data stream 202 at times determined by a write clock (WCLK) 204. Every time a pulse occurs on the write clock line 204, the current data on the data-in line 202 is stored in the memory location currently indicated by write address pointer 205, and the write address pointer 205 is incremented. The write clock (WCLK) 204 is derived from the data stream 202 (with some lag), and therefore may contain some jitter. (That is, individual ones of the pulses on the write clock line 204 may occur slightly sooner or slightly later than they should.) The read clock 206 similarly controls the timing of the read operations: every time a pulse occurs on the read clock line 206, data is read out from FIFO 200, from the location indicated by the read-address pointer 209. The read-address pointer 209 is then incremented. (Since the read clock 206 can be heavily filtered, using long-time information about the incoming signal, jitter is essentially absent from this clock.) A magnitude comparator 201 subtracts the value of the write-address pointer 205 from the value of the read-address pointer 209, to calculate jitter magnitude 203. If either the write address 205 or the read address 209 reaches its maximum value (determined by the size of the memory space in FIFO 200), it indicates an overflow (or underflow), and moves the read clock frequency to track the write clock until the overflow or underflow condition ceases. Note that the jitter will not be attenuated during the overflow or underflow condition, but data will be preserved. That is, if the write clock WCLK moves too much in relation to the read clock, an overflow or underflow can happen in the FIFO 200. The T1 standard (as defined by AT&T publication 62411, revised October 1985) sets the maximum peak to peak jitter movement at 28 Unit Intervals (UIs); the FIFO 200 will therefore normally have to be at least 28 bits deep.
The long-time average frequency of the write and read clocks 202 and 206 is 1.544 MHz in the T1 mode of operation, or 2.048 MHz in CEPT mode. T1 specifications and requirements are further detailed in AT&T publication, which defines jitter magnitude in terms of Unit Interval (UI), where 1 UI equals 1 clock period (for T1, 648 nsec) of phase slipping. The FIFO 200 can be imagined as a rubber band, which stretches and contracts relating to the reference frequency, to keep the data stream 202 (of data being written) coupled to the data stream 208 (of data being read), even though the two streams are partially asynchronous to each other.
The jitter also has a frequency component. The curve of maximum possible jitter magnitude versus frequency (in accordance with the T1 standard) is shown in FIG. 2B.
In the conventional architecture shown in FIG. 2A, the read clocks 206 and the write clocks 204 both typically have a frequency equal to the average data rate (which is 1.544 MHz for T1, or 2.048 MHz for CEPT). This limits the resolution of jitter reporting to 1 Unit Interval (1 UI). The FIFO could be operated at a multiple of the data rate if desired; this would give better resolution, but would require more memory space for the same maximum magnitude reporting.
The innovative teachings set forth herein permit the jitter magnitude reporting circuit to be simplified greatly. The write-address pointer 205 is sampled when the read-address pointer 209 goes through zero (i.e. reaches address 00000). This provides a jitter estimate (once for every 32 bits of data) which will be accurate to within one Unit Interval over the duration of four timeslots (32 bits, in the preferred embodiment). Moreover, no digital arithmetic circuits are needed, which greatly simplifies the implementation. (By contrast, a conventional circuit would typically use a subtraction circuit for comparator 201.)
This provides the advantage that less frequent sampling can be used. In the T1 standard, sampling every thirty-second bit implies a sampling rate of only 48.25 kHz. (Similarly, in the CEPT standard, sampling every thirty-second bit implies a sampling rate of only 64 kHz.)
This improved jitter estimating capability provides an improved capability for accurately receiving T1 signals (or for receiving signals in other communications formats.) FIG. 1 shows an example of a complete T1 interface, as enabled by one embodiment of the invention.
An example of previous attempts to configure an integrated circuit interface to the T1 line format can be seen in paper FAM21.2 from the 1987 ISSCC. This paper, by Kenneth Stern et al., of Crystal Semiconductor Corp., is entitled "A Monolithic Line Interface Circuit for T1 Terminals", and is hereby incorporated by reference.